Error correction and error detection methods are known which are used to increase the reliability of the operation of storage devices, for example DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), flash or EEPROM (Electrically Erasable Programmable Read-Only Memory) devices deployed in computers or in embedded systems. Such methods are usually based on EC/ED (EC: Error Correction, ED: Error Detection) codes for error correction and error detection.
A similar error correction and error detection method is based on known fundamental principles, such as those described by Richard W. Hemming: Error Detecting and Error Correcting Code, Bell System Technical Journal 29 (2): pp. 147-160, 1950. In order to secure, for example, n bit data with single bit error correction (SEC, single bit error correction), 1+log2 n code bits are required. For a so called double bit error detection (DED, Double Bit Error Detection), an extension by another bit is required. SEC/DED will thus together require (2+log2 n) code bits.
It is assumed that the probability that of the occurrence of each of the two possible errors, that is to say in the case of a storage process in a computer, an error resulting in 0 instead 1 or in 1 instead of 0, is always about the same.
This type of error correction and error detection is illustrated by FIG. 1, which shows 8 information data items D1-D8 to be stored in addition to 5 code data items C0-C4 so as to form one data word which is stored with a total of 13 bits. In this example, the code data value designated with C0 is used for DED.
For the information data D (8:1) to be stored, code data C (4:1) is determined according toD1×D2×D4×D5×D7→C1,D1×D3×D4×D6×D7→C2,D2×D3×D4×D8→C3 andD5×D6×D7×D8→C4,  (1)wherein the combination symbol “x” designates an evaluation of the data values D1-D8 of the information data D (8:1) to be stored as an X-OR combination. The status of the individual data values D1-D8 to be stored is in this case evaluated so that it is either determined whether an even parity exists, or determined whether an uneven parity exists. The DED code data value C0 is determined according toD1×D2×D3×D4×D5×D6×D7×D8→C0.  (2)
For the information data D(8:1) and code data C(4:1) read from a storage device, a syndrome S(4:1) having syndrome data values S1-S4 is determined according toC1×D1×D2×D4×D5×D7→S1,C2×D1×D3×D4×D6×D7→S2,C3×D2×D3×D4×D8→S3 andC4×D5×D6×D7×D8→S4, as well as  (3)C0×D1×D2×D3×D4×D5×D6×D7×D8→S0.  (4)
According to this method, the first four code data values C1-C4 and the first four syndrome data values S1-S4 are used for SEC, and the code and syndrome data values C0, S0 are used for DED. If the syndrome data values S0-S4 equal the value 0 in all 5 bits of the syndrome S(4:1, 0), no error has occurred during the storage and reading of the information data D(8:1). In the case of a single error, the first four SEC syndrome data S(4:1) indicate the position of the defective bit in the read data word (D(8:1), C(4:1)) and the DED syndrome data value S0 equals 1. In this case, the positions SP within the read data word (D(8:1), C(4:1)) in the row after the individual code data values and information data values are arranged in the sequence C1, C2, D1, C3, D2, D3, D4, C4, D5, D6, D7, D8. In the case of a double error, at least one bit of the SEC syndrome data S (4:1) is not equal to 0, while the DED syndrome data value S0 is equal to zero.
Such a method makes it possible to ensure in an advantageous manner that an error will be detected in a storage device during the reading of data from a storage device, and that it can be also corrected in the case of a single bit error.
A disadvantage in this case, however, is the requirement of significantly increased storage, which is needed not only for the information data values, but in addition also to secure the code data values. Increased computing resources are also required in order to determine the code data or the syndrome data. The determination of the code data and of the syndrome data is usually converted by means of coding and decoding hardware, which is a constituent part of a storage control unit.